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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xra1201/1201p 16-bit i2c/smbus gpio expander september 2011 rev. 1.0.0 general description the xra1201/1201p is a 16-bit gpio expander with an i 2 c/smbus interface. after power-up, the xra1201 has internal 100k ohm pull-up resistors on each i/o pin that can be individually enabled. the xra1201p has the internal pull-up resistors enabled upon power-up in case it is necessary for the inputs to be in a known state. in addition, the gpios on the xra1201/1201p can individually be controlled and configured. as outputs, the gpios can be outputs that are high, low or in three-state mode. the three-state mode feature is useful for applications where the power is removed from the remote devices, but they may still be connected to the gpio expander. as inputs, the internal pull-up resistors can be enabled or disabled and the input polarity can be inverted. the interrupt can be programmed for different behaviors. the interrupts can be programmed to generate an interrupt on the rising edge, falling edge or on bo th edges. the interrupt can be cleared if the input changes back to its original state or by reading the current state of the inputs. the xra1201/1201p are enhanced versions of other 16-bit gpio expanders with an i 2 c/smbus interface. the xra1201 is pin and software compatible with the pca9535, tca9535 and max7312. the xra1201p is pin and software compatible with the cat9555, pca9555, tca9555, max7311 and max7318. the xra1201/1201p are available in 24-pin qfn and 24-pin tssop packages. features ? 1.65v to 3.6v operating voltage ? 16 general purpose i/os (gpios) ? 5v tolerant inputs ? maximum stand-by current of 1ua at +1.8v ? i 2 c/smbus bus interface i 2 c clock frequency up to 400khz noise filter on sda and scl inputs up to 32 i 2 c slave addresses ? individually programmable inputs internal pull-up resistors polarity inversion individual interrupt enable rising edge and/or fa lling edge interrupt input filter ? individually programmable outputs output level control output three-state control ? open-drain active low interrupt output ? pin and software compatible with pca9535, tca9535, max7312 (xra1201) ? pin and software compatible with cat9555, pca9555, tca9555, max7311 and max7318 (xra1201p) ? 3kv hbm esd protection per jesd22-a114f ? 200ma latch-up performance per jesd78b applications ? personal digital assistants (pda) ? cellular phones/data devices ? battery-operated devices ? global positioning system (gps) ? bluetooth
xra1201/1201p 2 16-bit i2c/smbus gpio expander rev. 1.0.0 f igure 1. xra1201 b lock d iagram i 2 c/ smbus interface a2 a1 scl sda gpio control registers a0 ir q # p0 gpios p1 p2 p3 p4 p5 p6 p7 vcc (1.65v ? 3.6v) gnd p8 gpios p9 p10 p11 p12 p13 p14 p15 ordering information p art n umber p ackage n umber o f gpio s o perating t emperature r ange d evice s tatus xra1201il24-f qfn-24 16 -40c to +85c active xra1201il24tr-f qfn-24 16 -40c to +85c active xra1201pil24-f qfn-24 16 -40c to +85c active XRA1201PIL24TR-F qfn-24 16 -40c to +85c active xra1201ig24-f tssop-24 16 -40c to +85c active xra1201ig24tr-f tssop-24 16 -40c to +85c active xra1201pig24-f tssop-24 16 -40c to +85c active xra1201pig24tr-f tssop-24 16 -40c to +85c active n ote : tr = tape and reel, f = green / rohs f igure 2. p in o ut a ssignments xra1201/ xra1201p 24-pin qfn 78 9101112 gnd p8 p9 p10 p7 p6 17 18 13 16 14 15 p13 p14 p15 a0 p12 p11 24 23 22 21 20 19 2 1 6 3 5 4 p3 p2 p1 p0 p4 p5 irq# vcc sda scl a1 a2 xra1201/ xra1201p 24-pin tssop 3 5 4 7 6 8 9 10 11 12 1 2 13 14 15 16 17 18 19 20 21 22 23 24 irq# a1 a2 p0 p1 p2 p3 p4 p5 p6 p7 gnd vcc sda scl a0 p15 p14 p13 p12 p11 p10 p9 p8
xra1201/1201p 3 rev. 1.0.0 16-bit i2c/smbus gpio expander pin descriptions pin description n ame p in # p in # t ype d escription i 2 c interface sda 20 23 i/o i 2 c-bus data input/output (open-drain). scl 19 22 i i 2 c-bus serial input clock. irq# 22 1 od interrupt output (open-drain, active low). a0 a1 a2 18 23 24 21 2 3 i i i these pins select the i 2 c slave address. see table 1 . gpios p0 p1 p2 p3 p4 p5 p6 p7 1 2 3 4 5 6 7 8 4 5 6 7 8 9 10 11 i/o i/o i/o i/o i/o i/o i/o i/o general purpose i/os p0-p7. all gpio s are configured as inputs upon power- up or after a reset. after power-up or re set, the internal pull-up resistors are enabled for the xra1201p. the internal pull-up resistors are disabled for the xra1201. p8 p9 p10 p11 p12 p13 p14 p15 10 11 12 13 14 15 16 17 13 14 15 16 17 18 19 20 i/o i/o i/o i/o i/o i/o i/o i/o general purpose i/o p8-p15. all gpios are configured as inputs upon power- up or after a reset. after power-up or re set, the internal pull-up resistors are enabled for the xra1201p. the internal pull-up resistors are disabled for the xra1201. ancillary signals vcc 21 24 pwr 1.65v to 3.6v vcc supply voltage. gnd 9 12 pwr power supply common, ground. gnd center pad - pwr the exposed pad at the bottom surfac e of the package is designed for thermal performance. use of a center pad on th e pcb is strongly recommended for ther - mal conductivity as well as to provide mechanical stability of the package on the pcb. the center pad is recommended to be solder masked defined with open - ing size less than or equal to the exposed thermal pad on the package bottom to prevent solder bridging to the outer leads of the device. thermal vias must be connected to gnd plane as the therma l pad of package is at gnd potential. pin type: i=input, o=output, i/o= input/output, od=output open drain. qfn-24 tssop-24
xra1201/1201p 4 16-bit i2c/smbus gpio expander rev. 1.0.0 1.0 functional descriptions 1.1 i 2 c-bus interface the i 2 c-bus interface is compliant with the standard-mode and fast-mode i 2 c-bus specifications. the i 2 c-bus interface consists of two lines: serial data (sda) and serial clock (scl). in the standard-mode, the serial clock and serial data can go up to 100 kbps and in the fast-mode, the serial clock and serial data can go up to 400 kbps. the first byte sent by an i 2 c-bus master contains a start bit (sda tr ansition from high to low when scl is high), 7-bit slave address an d whether it is a read or write transacti on. the next byte is the sub-address that contains the address of the register to access. the xra120x responds to each write with an acknowledge (sda driven low by xra1201/1201p fo r one clock cycle when scl is high ). the last byte sent by an i 2 c- bus master contains a stop bit (sda transition from low to high when scl is high). see figures 3 - 5 below. for complete details, see the i 2 c-bus specifications. f igure 3. i c s tart and s top c onditions sda scl s p start condition stop condition f igure 4. m aster w rites t o s lave sw a a ap slave address command byte data byte white block: host to xra120x grey block: xra120x to host f igure 5. m aster r eads f rom s lave sw a ar slave address command byte white block: host to xra120x grey block: xra120x to host a s slave address ndata anap last data 2
xra1201/1201p 5 rev. 1.0.0 16-bit i2c/smbus gpio expander 1.1.1 i 2 c-bus addressing there could be many devices on the i 2 c-bus. to distinguish itself from the other devices on the i 2 c-bus, the xra1201/1201p has up to 32 i 2 c slave addresses using t he a2-a0 address lines. table 1 below shows the different addresses that can be selected. t able 1: i c a ddress m ap c a ddress gnd scl gnd 0x20 (0010 000x) gnd scl vcc 0x22 (0010 001x) gnd sda gnd 0x24 (0010 010x) gnd sda vcc 0x26 (0010 011x) vcc scl gnd 0x28 (0010 100x) vcc scl vcc 0x2a (0010 101x) vcc sda gnd 0x2c (0010 110x) vcc sda vcc 0x2e (0010 111x) gnd scl scl 0x30 (0011 000x) gnd scl sda 0x32 (0011 001x) gnd sda scl 0x34 (0011 010x) gnd sda sda 0x36 (0011 011x) vcc scl scl 0x38 (0011 100x) vcc scl sda 0x3a (0011 101x) vcc sda scl 0x3c (0011 110x) vcc sda sda 0x3e (0011 111x) gnd gnd gnd 0x40 (0100 000x) gnd gnd vcc 0x42 (0100 001x) gnd vcc gnd 0x44 (0100 010x) gnd vcc vcc 0x46 (0100 011x) vcc gnd gnd 0x48 (0100 100x) vcc gnd vcc 0x4a (0100 101x) vcc vcc gnd 0x4c (0100 110x) vcc vcc vcc 0x4e (0100 111x) gnd gnd scl 0x50 (0101 000x) gnd gnd sda 0x52 (0101 001x) gnd vcc scl 0x54 (0101 010x) gnd vcc sda 0x56 (0101 011x) vcc gnd scl 0x58 (0101 100x) vcc gnd sda 0x5a (0101 101x) vcc vcc scl 0x5c (0101 110x) vcc vcc sda 0x5e (0101 111x) 2 a2 a1 a0 i 2
xra1201/1201p 6 16-bit i2c/smbus gpio expander rev. 1.0.0 1.1.2 i 2 c read and write a read or write transaction is determined by bit-0 of the slave address. if bit-0 is ?0?, then it is a write transaction. if bit-0 is ?1?, then it is a read transaction. 1.1.3 i 2 c command byte an i 2 c command byte is sent by the i 2 c master following the slave address. the command byte indicates the address offset of the regist er that will be accessed. table 2 below lists the command bytes for each register. t able 2: i c c ommand b yte (r egister a ddress ) c ommand b yte r egister n ame d escription r ead /w rite d efault v alues 0x00 gsr1 - gpio state for p0-p7 read-only 0xxx 0x01 gsr2 - gpio state for p8-p15 read-only 0xxx 0x02 ocr1 - output control for p0-p7 read/write 0xff 0x03 ocr2 - output control for p8-p15 read/write 0xff 0x04 pir1 - input polarity inversion for p0-p7 read/write 0x00 0x05 pir2 - input polarity inversion for p8-p15 read/write 0x00 0x06 gcr1 - gpio configuration for p0-p7 read/write 0xff 0x07 gcr2 - gpio configuration for p8-p15 read/write 0xff 0x08 pur1 - input internal pull-up re sistor enable/disable for p0-p7 read/write 0x00 (xra1201) 0xff (xra1201p) 0x09 pur2 - input internal pull-up re sistor enable/disable for p8-p15 read/write 0x00 (xra1201) 0xff (xra1201p) 0x0a ier1 - input interrupt enable for p0-p7 read/write 0x00 0x0b ier2 - input interrupt enable for p8-p15 read/write 0x00 0x0c tscr1 - output three-state control for p0-p7 read/write 0x00 0x0d tscr2 - output three-state control for p8-p15 read/write 0x00 0x0e isr1 - input interrupt status for p0-p7 read 0x00 0x0f isr2 - input interrupt status for p8-p15 read 0x00 0x10 reir1 - input rising edge interrupt enable for p0-p7 read/write 0x00 0x11 reir2 - input rising edge interrupt enable for p8-p15 read/write 0x00 0x12 feir1 - input falling edge interrupt enable for p0-p7 read/write 0x00 0x13 feir2 - input falling edge interrupt enable for p8-p15 read/write 0x00 0x14 ifr1 - input filter enable/disable for p0-p7 read/write 0xff 0x15 ifr2 - input filter enable/disable for p8-p15 read/write 0xff 2
xra1201/1201p 7 rev. 1.0.0 16-bit i2c/smbus gpio expander 1.2 interrupts the table below summarizes the interrupt behavior of the different register sett ings for the xra1201/1201p. t able 3: i nterrupt g eneration and c learing b it b it b it b it b it i nterrupt g enerated b y : i nterrupt c leared b y : 1 0 x x x no interrupts enabled (default) n/a 1 1 0 0 0 a rising or falling edge on the input reading the gsr register or if the input changes back to its previous state (state of input during last read to gsr) 1 a rising or falling edge on the input and remains in the new state for more than 1075ns 1 1 1 0 0 a rising edge on the input reading the gsr register 1 a rising edge on the input and remains high for more than 1075ns 1 1 0 1 0 a falling edge on the input reading the gsr register 1 a falling edge on the input and remains low for more than 1075ns 1 1 1 1 0 a rising or falling edge on the input reading the gsr register 1 a rising or falling edge on the input and remains in the new state for more than 1075ns 0 x x x x no interrupts in output mode n/a gcr ier reir feir ifr
xra1201/1201p 8 16-bit i2c/smbus gpio expander rev. 1.0.0 2.0 register description 2.1 gpio state register 1 (gsr1) - read-only the status of p7 - p0 can be read via this register. a read will show the current state of these pins (or the inverted state of these pins if enabled via the pir regist er). reading this register will clear an input interrupt (see table 3 for complete details). reading th is register will also return th e last value written to the ocr register for any pins that are configured as outputs (ie. th is is not the same as the state of the actual output pin since the output pin can be in three-stat e mode). a write to this register has no effect. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.2 gpio state register 2 (gsr2) - read-only the status of p15 - p8 can be read via this register. a read will show the current state of these pins (or the inverted state of these pins if enabled via the pir regist er). reading this register will clear an input interrupt (see table 3 for complete details). reading th is register will also return th e last value written to the ocr register for any pins that are configured as outputs (ie. th is is not the same as the state of the actual output pin since the output pin can be in three-stat e mode). a write to this register has no effect. the msb of this register corresponds with p15 and the lsb of this register corresponds with p8. 2.3 output control register 1 (ocr1) - read/write when p7 - p0 are defined as outputs, they can be controlle d by writing to this regist er. reading this register will return the last valu e written to it, howeve r, this value may not be the actu al state of the output pin since these pins can be in three-state mode. the msb of th is register corresponds with p7 and the lsb of this register corresponds with p0. 2.4 output control register 2 (ocr2) - read/write when p15 - p8 are defined as outputs, they can be controlle d by writing to this regist er. reading this register will return the last valu e written to it, howeve r, this value may not be the actu al state of the output pin since these pins can be in three-state mode. the msb of th is register corresponds with p15 and the lsb of this register corresponds with p8. 2.5 input polarity inversion register 1 (pir1) - read/write when p7 - p0 are defined as inputs, this register inverts the polarity of the input value read from the input port register. if the corresponding bit in this register is set to ?1?, the va lue of this bit in the gsr register will be the inverted value of the input pin. if the corresponding bit in this register is se t to ?0?, the value of this bit in the gsr register will be the actual value of the input pin. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.6 input polarity inversion register 2 (pir2) - read/write when p15 - p8 are defined as inputs, this register inverts the polarity of the input value read from the input port register. if the corresponding bit in this register is set to ?1?, the va lue of this bit in the gsr register will be the inverted value of the input pin. if the corresponding bit in this register is se t to ?0?, the value of this bit in the gsr register will be the actual value of the input pin. the msb of this register corresponds with p15 and the lsb of this register corresponds with p8. 2.7 gpio configuration register 1 (gcr1) - read/write this register configures the gpios as inputs or out puts. after power-up and reset, the gpios are inputs. setting these bits to ?0? will enable t he gpios as outputs. setting these bits to ?1? will enable the gpios as inputs. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.8 gpio configuration register 2 (gcr2) - read/write this register configures the gpios as inputs or out puts. after power-up and reset, the gpios are inputs. setting these bits to ?0? will enable t he gpios as outputs. setting these bits to ?1? will enable the gpios as inputs. the msb of this register corresponds with p 15 and the lsb of this register corresponds with p8.
xra1201/1201p 9 rev. 1.0.0 16-bit i2c/smbus gpio expander 2.9 input internal pull-up enable/disable register 1 (pur1) - read/write this register enables/disables the internal pull-up resistors for an input. after power-up and reset, the internal pull-up resistors are disabled for the xra1201. writing a ?1? to th ese bits will enable the internal pull-up resistors. after power-up and reset, the internal pull-up resistors are enabled for the xra1201p. writing a ?0? to these bits will disable the internal pull-up resistors. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.10 input internal pull-up enable/disable register 2 (pur2) - read/write this register enables/disables the internal pull-up resistors for an input. after power-up and reset, the internal pull-up resistors are disabled for the xra1201. writing a ?1? to th ese bits will enable the internal pull-up resistors. after power-up and reset, the internal pull-up resistors are enabled for the xra1201p. writing a ?0? to these bits will disable the internal pull-up resistors. the msb of this register co rresponds with p15 and the lsb of this register corresponds with p8. 2.11 input interrupt enable register 1 (ier1) - read/write this register enables/disables the interrupts for an inpu t. after power-up and reset, the interrupts are disabled. writing a ?1? to these bits will enable the interrupt for the corresponding input pins. see table 3 for complete details of the interrupt behavior for various register se ttings. no interrupts are generated for outputs when gcr bit is 0. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.12 input interrupt enable re gister 2 (ier2) - read/write this register enables/disables the interrupts for an inpu t. after power-up and reset, the interrupts are disabled. writing a ?1? to these bits will enable the interrupt for the corresponding input pins. see table 3 for complete details of the interrupt behavior for various register se ttings. no interrupts are generated for outputs when gcr bit is 0. the msb of this register corresponds with p 15 and the lsb of this register corresponds with p8. 2.13 output three-state control register 1 (tscr1) - read/write this register can enable/disable the three-state mode of an output. writ ing a ?1? to these bits will enable the three-state mode for the corresponding output pins. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.14 output three-state control register 2 (tscr2) - read/write this register can enable/disable the three-state mode of an output. writ ing a ?1? to these bits will enable the three-state mode for the corresponding output pins. th e msb of this register corresponds with p15 and the lsb of this register corresponds with p8. 2.15 input interrupt status register 1 (isr1) - read-only this register reports the input pins that have generated an interrupt. see table 3 for complete details of the interrupt behavior for various register settings. the m sb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.16 input interrupt status register 2 (isr2) - read-only this register reports the input pins that have generated an interrupt. see table 3 for complete details of the interrupt behavior for various register settings. the msb of this register corresponds with p15 and the lsb of this register corresponds with p8.
xra1201/1201p 10 16-bit i2c/smbus gpio expander rev. 1.0.0 2.17 input rising edge interrupt enable register 1 (reir1) - read/write writing a ?1? to these bits will enable the corresponding input to generate an interrupt on the rising edge. see table 3 for complete details of th e interrupt behavior for various register settings. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.18 input rising edge interrupt enable register 2 (reir2) - read/write writing a ?1? to these bits will enable the corresponding input to generate an interrupt on the rising edge. see table 3 for complete details of th e interrupt behavior for various register settings. the msb of this register corresponds with p15 and the lsb of this register corresponds with p8. 2.19 input falling edge interrupt enab le register 1 (feir1) - read/write writing a ?1? to these bits will enabl e the correspondi ng input to generat e an interrupt on the falling edge. writing a ?1? to these bits will make that input generate an interrup t on the rising edge only. see table 3 for complete details of the interrupt behavior for various re gister settings. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.20 input falling edge interrupt enab le register 2 (feir2) - read/write writing a ?1? to these bits will enabl e the correspondi ng input to generat e an interrupt on the falling edge. writing a ?1? to these bits will make that input generate an interrup t on the rising edge only. see table 3 for complete details of the interrupt behavior for various re gister settings. the msb of this register corresponds with p15 and the lsb of this r egister corresponds with p8. 2.21 input filter enable regi ster 1 (ifr1) - read/write by default, the input filters are enabled (ifr = 0xff). when the input filters are enabled, any pulse that is greater than 1075ns will generate an interr upt (if enabled). pulses that are le ss than 225ns will be filtered and will not generate an interr upt. pulses in between this range may or may no t generate an interr upt. writing a ?0? to these bits will disable the input filter for the corresponding inputs. with the input filters disabled, any change on the inputs will generate an interrupt (if enabled). see table 3 for complete details of the interrupt behavior for various register settings. the msb of this regist er corresponds with p7 and the lsb of this register corresponds with p0. 2.22 input filter enable regi ster 2 (ifr2) - read/write by default, the input filters are enabled (ifr = 0xff). when the input filters are enabled, any pulse that is greater than 1075ns will generate an interr upt (if enabled). pulses that are le ss than 225ns will be filtered and will not generate an interr upt. pulses in between this range may or may no t generate an interr upt. writing a ?0? to these bits will disable the input filter for the corresponding inputs. with the input filters disabled, any change on the inputs will generate an interrupt (if enabled). see table 3 for complete details of the interrupt behavior for various register settings. the msb of this register corresponds with p15 and the lsb of this register corresponds with p8.
absolute maximum ratings power supply voltage 3.6 volts supply current 160 ma ground current 200 ma external current limit of each gpio 25 ma total current limit for gpio[15:8] and gpio[7:0] 100 ma total current limit for gpio[15:0] 200 ma total supply current sourced by all gpios 160 ma operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c power dissipation 200 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (24-qfn) theta-ja = 38 o c/w, theta-jc = 26 o c/w thermal resistance (24-tssop) theta-ja = 84 o c/w, theta-jc = 16 o c/w xra1201/1201p 11 rev. 1.0.0 16-bit i2c/smbus gpio expander
electrical characteristics dc electrical characteristics u nless otherwise noted : ta = -40 o to +85 o c, v cc is 1.65v to 3.6v s ymbol p arameter l imits r m in m ax l imits r m in m ax l imits r m in m ax u nits c onditions v il input low voltage -0.3 0.3vcc -0.3 0.3vcc -0.3 0.3vcc v note 1 v il input low voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 v note 2 v ih input high voltage 1.3 vcc 1.8 vcc 2.3 vcc v note 1 v ih input high voltage 1.4 5.5 1.8 5.5 2.0 5.5 v note 2 v ol output low voltage 0.4 0.4 0.4 v v v i ol = 3 ma i ol = 3 ma i ol = 3 ma note 3 v ol output low voltage 0.5 0.5 0.5 v i ol = 8 ma note 4 v ol output low voltage 0.4 0.4 0.4 v v v i ol = 6 ma i ol = 4 ma i ol = 1.5 ma note 5 v oh output high voltage 1.2 1.8 2.6 v v v i oh = -8 ma i oh = -8 ma i oh = -8 ma note 4 i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua c in input pin capacitance 5 5 5 pf i cc power supply current 50 100 200 ua test 1 i cc power supply current 150 250 500 ua test 2 i ccs standby current 1 2 5 ua test 3 r gpio gpio pull-up resistance 60 140 60 140 60 140 k : 100k : r 40% xra1201/1201p 12 16-bit i2c/smbus gpio expander rev. 1.0.0 n otes : 1. for i 2 c input signals (sda, scl); 2. for gpios, a0, a1 and a2 signals; 3. for i 2 c output signal sda; 4. for gpios; 5. for irq# signal; 1.8v 10% 2.5v 10% 3.3v 10%
xra1201/1201p 13 rev. 1.0.0 16-bit i2c/smbus gpio expander test 1: scl frequency is 400 khz with internal pull-ups disabled. all gpios are configured as inputs. all inputs are steady at vcc or gnd. outputs are fl oating or in the tri-state mode. test 2: scl frequency is 400 khz with internal pull-ups enabl ed. all gpios are configured as inputs. all inputs are steady at vcc or gnd. outputs are fl oating or in the tri-state mode. test 3: all inputs are steady at vcc or gnd to minimize stan dby current. if internal pull-up is enabled, input voltage level should be the same as vcc. all gpios are configured as inpu ts. scl and sda are at vcc. ou tputs are left floating or in tri-state mode. ac electrical characteristics unless otherwise noted: ta=-40 o to +85 o c, vcc=1.65v - 3.6v s ymbol p arameter s tandard m ode c-b us m in m ax f ast m ode c-b us m in m ax u nit f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start 4.7 1.3 p s t hd;sta start condition hold time 4.0 0.6 p s t su;sta start condition setup time 4.7 0.6 p s t hd;dat data hold time 0 0 ns t vd;ack data valid acknowledge 0.6 0.6 p s t vd;dat scl low to data out valid 0.6 0.6 ns t su;dat data setup time 250 150 ns t low clock low period 4.7 1.3 p s t high clock high period 4.0 0.6 p s t f clock/data fall time 300 300 ns t r clock/data rise time 1000 300 ns t sp pulse width of spikes tolerance 50 50 ns t d1 i 2 c-bus gpio output valid 0.2 0.2 p s t d4 i 2 c input pin interrupt valid 4 4 p s t d5 i 2 c input pin interrupt clear 4 4 p s t d15 scl delay after reset 3 3 p s i 2 i 2
f igure 6. i c-b us t iming d iagram start condition (s) bit 7 msb (a7) bit 6 (a6) protocol t buf t r t su;sta t low t high 1/f scl t f scl t hd;sta t su;dat t hd;dat sda bit 0 lsb (r/w) acknowledge (a) stop condition (p) t vd;dat t sp t vd;ack t su;sto f igure 7. w rite t o o utput slave address wa command byte adataa sda gpion t d1 f igure 8. gpio p in i nterrupt slave address wa command byte adata a sda int# t d5 ra slave address s px t d4 p ack from slave ack from slave ack from m aster xra1201/1201p 14 16-bit i2c/smbus gpio expander rev. 1.0.0 2
package dimensions (24 pin qfn - 4 x 4 x 0.9 mm ) note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm t note: the control dimension is in millimeter. a - 0.039 - 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 t 0 14 o 0 14 o d 0.154 0.161 3.90 4.10 d2 0.087 0.102 2.20 2.60 b 0.007 0.012 0.18 0.30 e 0.020 bsc 0.50 bsc l 0.012 0.020 0.30 0.50 k 0.008 - 0.20 - xra1201/1201p 15 rev. 1.0.0 16-bit i2c/smbus gpio expander inches millimeters symbol min max min max
package dimensions (24 pin tssop - 4.4 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.047 0.80 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.2 d 0.303 0.311 7.70 7.90 e 0.240 0.264 6.10 6.70 e1 0.169 0.177 4.30 4.50 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 d 0 8 0 8 xra1201/1201p 16 16-bit i2c/smbus gpio expander rev. 1.0.0
revision history d ate r evision d escription september 2011 1.0.0 final datasheet. 17 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2011 exar corporation datasheet september 2011. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xra1201/1201p rev. 1.0.0 16-bit i2c/smbus gpio expander

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